Gallium nitride (GaN) is a III-V compound semiconductor formed by combining gallium (group III) and nitrogen (group V) elements. GaN crystallizes in a wurtzite hexagonal structure, as shown in Fig. 1. Each Ga atom contributes three valence electrons, while each N atom contributes five, forming strong covalent bonds. This robust crystal structure imparts GaN with a wide bandgap (~3.4 eV), high breakdown electric field (~3.3 MV/cm), and excellent thermal conductivity (~1.3 W/(cm·K)) [14].

These intrinsic properties make GaN suitable for high-power and high-frequency applications. Figure 2 compares key physical parameters such as bandgap, electron mobility, and thermal conductivity among GaN, GaAs, InP, and SiC. Notably, GaN offers a superior combination of wide bandgap and high electron saturation velocity, which enables faster switching and higher efficiency in power devices [5].

Figure 1.

A wurtzite crystal structure of GaN [14]

Figure 2.

An overview of physical material parameters based on silicon carbide, germanium and gallium nitride [5, 14]

GaN-based MOSFETs represent a transformative leap in power semiconductor technology. These devices outperform traditional Si-based MOSFETs in voltage, frequency, and temperature endurance due to GaN’s wide bandgap and high electron mobility (~2000 cm²/(V·s)) [15].

Figure 3a shows the structural overview of a GaN MOSFET, and Fig. 3b provides a cross-sectional view. The primary components include the GaN substrate, source, drain, gate, and gate oxide. Each plays a crucial role in device performance:

• GaN substrate: Acts as the base layer; its high critical electric field (~3.3 MV/cm) supports elevated breakdown voltages.

• Source/Drain (S/D): Enable electron injection and collection, respectively.

• Gate (G): Controls the conductive channel by modulating electric fields across the gate oxide.

• Oxide layer: Typically made from high-κ materials like Al₂O₃ or HfO₂, this insulator prevents gate leakage and enables high-speed switching.

The operational principle is similar to conventional MOSFETs: gate voltage modulates the conductive channel between source and drain. However, GaN devices can operate at frequencies >10 MHz and voltages >600 V with reduced on-resistance (R_on < 50 mΩ·mm) [16, 17].

GaN MOSFETs are widely employed in applications such as:

– Power converters: High-efficiency DC-DC and AC-DC converters

– RF systems: Low-noise amplifiers and RF switches

– Electric vehicles: Onboard chargers and inverters

Their high-power density (>10 W/mm²) allows for compact and lightweight systems, critical in aerospace, automotive, and renewable energy sectors [18].

By replacing Si-based devices in high-power applications, GaN MOSFETs enable higher efficiency, lower thermal losses, and reduced cooling requirements. These attributes mark them as key enablers in next-generation electronic systems.

Figure 3.

(a) GaN MOSFET, (b) a side view of a GaN substrate MOSFET

Dopant profile characterization is essential for validating the electrical behavior, reliability, and security of GaN MOSFETs. It ensures uniform charge carrier distribution, influences threshold voltage control, and mitigates adverse effects such as punch-through leakage, mobility degradation, and threshold voltage drift [7]. Moreover, dopant uniformity is vital for cryptographic applications where timing consistency and resistance to tampering are critical.

Spreading resistance profiling (SRP) and finite element analysis (FEA) are combined to evaluate dopant behavior in GaN devices. SRP measures voltage drops under known current flow across microprobes in contact with the device surface, correlating resistance changes to dopant concentration [13]. This technique provides vertical profiling resolution on the order of tens of nanometers. Finite element analysis is used to simulate electric potential and carrier transport using the Poisson and continuity equations under applied bias. Parameters such as dopant gradient steepness and junction depth are extracted and verified against SRP data. This hybrid approach supports accurate modeling of GaN MOSFET behavior across operating conditions and layout geometries.

Precision in dopant profiling impacts several aspects:

• Ensures threshold voltage stability across operating temperatures.

• Detects anomalies from processing steps such as implantation damage.

• Supports design optimization for reduced short-channel effects.

• Assess doping-related variations that could be exploited in hardware security attacks.

As GaN devices scale down, maintaining tight control of doping profiles becomes essential for ensuring predictable electrical performance and long-term reliability.

Figure 4 outlines the flowchart of the dopant profile testing methodology. Devices based on GaAs, InP, and GaN were chosen for benchmarking based on their contrasting bandgaps and mobility properties. SRP measurements were performed under room temperature (25 °C) using high-precision microprobes. The results were input into FEA simulations, developed in Sentaurus TCAD, which modeled dopant-dependent electric field distribution. Capacitance-voltage (C–V) analysis was conducted across a sweep of gate voltages to determine interface trap density, depletion width, and flat-band voltage. The combined use of SRP, FEA, and C–V profiling yields a comprehensive map of doping behavior and field effects across device architectures.

Figure 4.

Flowchart of dopant profile testing

Experimental setups were equipped with thermal stages to maintain test temperature stability within ±0.5 °C. GaN MOSFETs were subjected to fixed drain bias while the gate voltage was modulated incrementally. Capacitance measurements were performed using an LCR meter with a 1 MHz test frequency. The test conditions mimicked real-world switching environments to assess device resilience. Data from SRP were cross-referenced with FEA-extracted profiles, ensuring fidelity in dopant gradient reconstruction. C–V-derived depletion region widths were used to validate built-in potential models and confirm doping depths. This approach ensures high-resolution, multidimensional evaluation of dopant effects in compound semiconductor MOSFETs.

The combination of FEA and SRP offers a robust method for analyzing doping profiles in semiconductor devices, including dopant concentration, channel length, threshold voltage, and material parameters. FEA solves the Poisson equation, linking electric potential, charge density, and permittivity, to calculate the electric potential distribution and dopant concentration within device structures [35]. This enables comprehensive dopant profile simulations for materials like GaAs, InP, and GaN MOSFETs [16].

From Fig. 5, the output of MOSFETs made from GaAs, InP, and GaN by plotting the drain current (I_D) against the drain voltage (V_D) at a constant gate-source voltage (V_gs = 2 V) with running drain voltage (V_D). The GaN MOSFET, represented by the blue dashed line, exhibits the highest drain current among the three materials, reaching a saturation current (I_on) of approximately 450 µA. This indicates that GaN has the best performance in terms of current conduction. The GaAs MOSFET, shown by the black dashed line, has a saturation current of about 400 µA, while the InP MOSFET, indicated by the red dashed line, reaches a saturation current of around 350 µA. These differences highlight the superior electron mobility and material properties of GaN compared to GaAs and InP, making GaN the best choice for achieving higher drive currents in MOSFET applications.

Figure 6 compares the transfer characteristics of GaAs, InP, and GaN MOSFETs under a uniform drain voltage condition (V_D = 2 V) with running gate voltage (V_G). The blue curve representing the GaN MOSFET demonstrates superior performance, with the highest on-state current (I_on) of approximately 475 µA and a reduced on-state resistance (R_on ≈ 4.21 Ω) compared to the other semiconductor materials. In contrast, the GaAs MOSFET showcases an on-state current of about 450 µA and an on-state resistance of roughly 4.44 Ω. Conversely, the InP MOSFET exhibits the lowest on-state current at around 400 µA and an on-state resistance of approximately 5 Ω. Remarkably, all three devices exhibit minimal off-state current (I_off) at a gate voltage of 0 V, resulting in notably high off-state resistance (R_off). This evaluation highlights the superior characteristics of GaN in achieving increased current conduction and reduced on-state resistance, positioning it as the preferred choice for high-performance MOSFET applications. FEA is used to simulate complex physical systems with intricate geometries and varying conditions, offering insights into material and structural behavior under stress, strain, and temperature [35]. This helps improve designs and performance while reducing the need for costly prototypes, saving time and resources. Its integration with TCAD tools enhances analysis during the design phase. For compound semiconductors and MOSFETs, FEA is crucial in predicting device responses to electrical and thermal stresses, improving reliability and effectiveness [35]. Using first-order FEA for drain current vs. drain voltage and gate voltage, reliability is analyzed with Eqs (1) and (2).

$A=\frac{h}{2}[f(a)+f(b)];$ (1)

$\sum _{i=1}^{n}wf(x),$ (2)

In Fig. 7 3D bar chart compares the FEA values for three semiconductor materials: GaN, GaAs, and InP. The x-axis represents the materials, the y-axis represents the electric field in V/m², and the z-axis represents the FEA values in I_D(A). GaN demonstrates the highest FEA value of 3.0 A at an electric field of 1.5 V/m². GaAs follows with an FEA value of 2.0 A at an electric field of 1.0 V/m². InP shows the lowest FEA value of 1.0 A at an electric field of 0.5 V/m². This chart highlights that GaN has the strongest field effect response, followed by GaAs and InP, under the specified electric field conditions.

The provided Fig. 8 illustrates the transfer characteristics (I_D vs V_G) and transconductance (g_m vs V_G) for MOSFETs utilizing GaAs, InP and GaN semiconductor materials, with a constant drain voltage (V_D = 2 V) and a gate length (L_G) of 200 nm.

The GaAs MOSFET (black line) demonstrates a steady increase in drain current (I_D) with increasing gate voltage (V_G), peaking at around 400 µA. Its transconductance (g_m) also increases to a maximum value of approximately 350 µS before declining. The InP MOSFET (red line) similarly shows an increase in drain current with gate voltage, reaching a peak of approximately 350 µA, while its peak transconductance is around 300 µS. The GaN MOSFET (blue line), however, outperforms both GaAs and InP MOSFETs by achieving the highest peak drain current of around 450 µA and a peak transconductance of approximately 400 µS. These values are tabled in Table 1 as shown in below.

Figure 5.

Drain current versus drain voltage of GaAs, InP and GaN substrate

Figure 6.

Drain current versus gate voltage of GaAs, InP and GaN substrate

Figure 7.

FEA of drain current versus drain voltage of GaAs, InP and GaN substrate from Fig. 5

Figure 8.

Drain current versus gate voltage versus transconductance of GaAs, InP and GaN substrate

Figure 9 explains a Colpitts oscillator circuit using a GaN MOSFET, known for its efficiency and high-frequency performance. In this circuit, the GaN MOSFET acts as the active component, with two capacitors in series forming part of the resonant tank circuit, coupled with an inductor. This LC circuit determines the oscillation frequency. The feedback for sustaining oscillations is provided by the capacitors' voltage division, sending a portion of the output signal back to the MOSFET's gate. AC voltage sources are included: one for initiating oscillation at the gate and the other for delivering the output via the drain. Ground connections ensure stability, generating a consistent high-frequency signal utilizing the GaN MOSFET's capabilities. The Eq. (3) representing the built-in potential (V_bi) is a crucial parameter in the context of a MOSFET based on a GaAs, InP and GaN substrate, serving as a quantitative indicator of the potential variance across the junction established between the gate oxide and the graphene channel.

$V_{bi}=\frac{kT}{q}\ln \left(\frac{N_D{N}_A}{n_i^2}\right),$ (3)

where V_bi is built-in potential of the junction, k = 1.38∙10^-23 J/K (Boltzmann constant), T = 298 K (temperature in Kelvin), q = 1.6∙10^-19 C (electron charge), N_D is the donor concentration, N_A is the acceptor concentration, n_i is intrinsic carrier concentration

The built-in potential (V_bi) is crucial for several reasons. First, it creates equilibrium in the MOSFET, preventing further charge carrier diffusion and ensuring stable device operation. This equilibrium is essential for proper functionality. Second, V_bi directly impacts the threshold voltage (V_th), the minimum gate voltage needed to invert the semiconductor surface and form a conductive channel between the source and drain. Additionally, the built-in potential affects the C–V characteristics [7], which are important for understanding gate capacitance and switching behavior. This helps engineers optimize doping levels and material properties for better electrical efficiency, enhancing device configuration for specific applications. A well-defined V_bi also reduces short-channel effects in smaller MOSFETs, improving switching speeds and power efficiency for high-performance applications

$w=\sqrt{\frac{2{\epsilon }_s(V_{bi}-V_{gs})}{q_{N_D}}},$ (4)

were, w is depletion width in the semiconductor, ε_s is permittivity of the semiconductor material, V_bi is built-in potential of the junction, V_gs is gate-to-source voltage, q = 1.6∙10^-19 C (electron charge), N_D is donor concentration, representing the concentration of donor atoms in the n-type semiconductor region.

The calculation of the depletion width w in the semiconductor region of a MOSFET is determined by a specific Eq. (4). This equation is formulated based on Poisson's equation, which establishes a relationship between the charge density and the electric field within a semiconductor. The depletion width signifies the area in the semiconductor where there is a reduction in mobile charge carriers due to the presence of an applied electric field.

Figure 10 shows the variation of the gate-source capacitance (C_gs) as a function of gate-source voltage (V_gs) for three different semiconductor materials: GaAs, InP, and GaN, at a doping concentration (N_D) of 1∙15 at 25 °C. The curves indicate that C_gs changes with V_gs for each material, demonstrating a distinct minimum point. GaAs and InP exhibit similar capacitance profiles, with capacitance decreasing to a minimum around 0 before increasing symmetrically. In contrast, GaN shows a wider and more pronounced minimum, indicating a different capacitance behavior and potentially higher sensitivity to V_gs changes, which can be advantageous in high-frequency and high-power applications

$c_d=\frac{{\epsilon }_s}{w}.$ (5)

In a MOSFET, the formation of the depletion region occurs upon the application of a voltage to the gate terminal. This results in the generation of an electric field that causes a reduction in the number of free charge carriers near the interface between the semiconductor and oxide layers. From Eq. (5), the depletion capacitance (C_D) emerges from this specific region and exhibits an inverse relationship with the width (w) of the depletion region. For smaller values of w, the depletion region tends to be narrower, leading to a higher value of capacitance C_D. Conversely, when w is increased, the depletion region widens, resulting in a decrease in the capacitance C_D. Understanding this correlation is essential for comprehending the impact of gate voltage on the behavior of the MOSFET, particularly within the threshold region where the device transitions between the off-state and the on-state. The depletion capacitance plays a significant role in determining the total capacitance observed at the gate, thereby influencing the switching characteristics and frequency response of the MOSFET.

The Fig. 11 illustrates the correlation between depletion capacitance (C_D) and gate-source voltage (V_gs) for three distinct semiconductor materials: GaAs, InP, and GaN, at a doping concentration (N_D) of 1∙15 at 25 °C. The plotted curves demonstrate the variation of depletion capacitance in response to the applied gate-source voltage for each material. GaAs and InP exhibit similar trends, characterized by sharp capacitance peaks at specific V_GS levels, indicating regions of rapid depletion width alteration. Conversely, GaN displays a broader and less prominent peak, implying a contrasting capacitance behavior and depletion region reaction to the gate voltage. This disparity in capacitance attributes is a manifestation of the unique material characteristics of GaN, which could potentially impact its efficacy in applications involving high-frequency and high-power scenarios in comparison to GaAs and InP.

Figure 9.

Small-signal diagram of the GaN MOSFET capacitance vs voltage

Figure 10.

Gate capacitance versus gate voltage of GaAs, InP and GaN substrate

Variability and uniformity testing in MOSFETs are essential for ensuring consistent performance across manufacturing batches and wafers [7]. Key tests focus on V_th and g_m across different gate lengths, potential variations, and dopant concentrations. V_th testing measures how changes in gate length, potential, and doping affect V_th, helping manage short-channel effects and electrical stress. Consistent V_th under varying conditions indicates stable manufacturing and effective doping control. Parameter g_m testing measures the change in drain current with gate voltage, assessing the device’s amplification capacity. Analyzing g_m under different conditions ensures uniform amplification and reveals the stability of the manufacturing process. Testing V_th and g_m ensures minimal variability and high consistency, improving the reliability and performance of MOSFETs in integrated circuits.

$V_{th}=V_{fb}+2{\varphi }_F+\frac{Q_D}{C_{ox}};$ (6)

${\varphi }_F=\frac{kT}{q}\ln \left[\frac{N_A}{n_i}\right];$ (7)

Q _D = qN_Ax_dT; (8)

$C_{ox}=\frac{{\epsilon }_{ox}}{t_{ox}}$ (9)

where V_th is threshold voltage, V_fb is flat band voltage, ϕ_F is potential difference, Q_D is charge in the depletion region, C_ox is gate oxide capacitance, k is Boltz man constant, T is temperature, N_A is dopant concentration and n_i is intrinsic carrier concentration, x_d is maximum depletion width (cm), ε_ox is permittivity of oxide and t_ox is oxide thickness (cm).

From Eqs (6)–(9) the threshold voltage (V_th) of a MOSFET is defined as the minimum gate-source voltage required to establish a conductive channel between the source and drain terminals. This threshold voltage is influenced by various factors: the flat-band voltage (V_fb), which compensates for disparities in work function between the gate material and the semiconductor; twice the Fermi potential (2ϕ_F), which guarantees that the surface potential is adequate to induce inversion in the semiconductor surface and create a conductive channel; and the term Q_D, C_ox, which denotes the extra gate voltage necessary to equalize the charge in the depletion region (Q_D) with the induced charge on the gate, where C_ox represents the capacitance of the gate oxide layer. Collectively, these factors ascertain the gate voltage required to activate the MOSFET, underscoring the significance of this equation in comprehending and formulating MOSFET devices.

The Fig. 12 illustrates the relationship between the Fermi potential (Φ_F) and the acceptor concentration (N_A) for three semiconductor materials: InP, GaN, and GaAs. The x-axis represents the acceptor concentration (N_A) on a logarithmic scale ranging from 1∙10¹⁶ to 1∙10¹⁹ cm^-3, while the y-axis shows the Fermi potential (Φ_F) in volts (V), ranging from 0.45 to 0.80 V. The data points for InP, GaN, and GaAs are represented by black squares, red circles, and blue triangles, respectively. For InP, the Fermi potential increases linearly with the acceptor concentration, starting around 0.50 V at N_A = 1∙10¹⁶ cm^-3 and reaching approximately 0.65 V at N_A = 1∙10¹⁹ cm^-3 GaN exhibits a more rapid increase, with the Fermi potential starting around 0.55 V at N_A = 1∙10¹⁶ cm^-3 and reaching about 0.75 V at N_A = 1∙10¹⁹ cm^-3. GaAs shows an intermediate behavior, with the Fermi potential starting around 0.60 V at N_A = 1∙10¹⁶ cm^-3 and reaching approximately 0.78 V at N_A = 1∙10¹⁹ cm^-3. These observations indicate that GaN has the highest increase in Fermi potential with increasing acceptor concentration, making it more sensitive to doping levels compared to InP and GaAs. This data is crucial for optimizing the electrical properties of semiconductor devices.

The Fig. 13 illustrates the relationship between the gate length (L_G) of a MOSFET and two key parameters: V_th and g_m. The x-axis represents the gate length (L_G) in nanometers (nm), ranging from 120 to 200 nm. The left y-axis shows the V_th in volts (V), ranging from 1.30 to 1.75 V, while the right y-axis indicates the g_m in mS, ranging from 0.25 to 0.70 mS. The cyan line depicts the threshold voltage, which decreases with increasing gate length, starting at approximately 1.75 V for a gate length of 120 nm and dropping to around 1.35 V for a gate length of 200 nm. Conversely, the green line represents the transconductance, which increases with gate length, starting at about 0.30 mS for a gate length of 120 nm and rising to around 0.65 mS for a gate length of 200 nm. This Fig. 13 highlights the inverse relationship between the threshold voltage and transconductance concerning the gate length. As the gate length increases, the threshold voltage decreases, indicating a lower voltage required to turn on the MOSFET, while the transconductance increases, reflecting an improved ability of the MOSFET to control the output current. The intersections and marked circles on the graph suggest points of particular interest or significant changes in the trends, crucial for optimizing MOSFET performance in various applications.

The Table 2 describes the distinct properties of GaAs, InP, and GaN regarding their threshold voltages and consistency. GaN emerges as the most notable due to its highest average V_th and the least standard deviation, rendering it well-suited for applications requiring high power and high uniformity. InP, on the other hand, presents the lowest average V_th, making it appropriate for low-power applications, albeit with moderate consistency. In contrast, GaAs exhibits a high average V_th but displays more variability, necessitating stricter control during the manufacturing process to ensure reliable performance.

Figure 11.

Depletion capacitance versus gate voltage of GaAs, InP and GaN substrate

Figure 12.

Potential difference versus dopant concentration of GaAs, InP and GaN substrate

Figure 13.

Threshold voltage and transconductance with varying gate length of GaN substrate