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  <front>
    <journal-meta>
      <journal-id journal-id-type="publisher-id">80</journal-id>
      <journal-id journal-id-type="index">urn:lsid:arphahub.com:pub:3CDB4662-2EEC-55B0-878A-88F876A7F403</journal-id>
      <journal-title-group>
        <journal-title xml:lang="en">Modern Electronic Materials</journal-title>
        <abbrev-journal-title xml:lang="en">MoEM</abbrev-journal-title>
      </journal-title-group>
      <issn pub-type="ppub">2452-2449</issn>
      <issn pub-type="epub">2452-1779</issn>
      <publisher>
        <publisher-name>NUST MISiS</publisher-name>
      </publisher>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="doi">10.3897/j.moem.5.1.38575</article-id>
      <article-id pub-id-type="publisher-id">38575</article-id>
      <article-categories>
        <subj-group subj-group-type="heading">
          <subject>Research Article</subject>
        </subj-group>
      </article-categories>
      <title-group>
        <article-title>Getters in silicon</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author" xlink:type="simple" corresp="yes">
          <name name-style="western">
            <surname>Kharchenko</surname>
            <given-names>Vyacheslav A.</given-names>
          </name>
          <xref ref-type="aff" rid="A1">1</xref>
          <email xlink:type="simple">vakh41@mail.ru</email>
        </contrib>
      </contrib-group>
      <aff id="A1">
        <label>1</label>
        <addr-line content-type="verbatim">Dorodnicyn Computing Centre, Federal Research Center «Computer Science and Control» of Russian Academy of Sciences, 40 Vavilov Str., Moscow 119333, Russia</addr-line>
        <institution>Federal Research Center «Computer Science and Control» of Russian Academy of Sciences</institution>
        <addr-line content-type="city">Moscow</addr-line>
        <country>Russia</country>
      </aff>
      <author-notes>
        <fn fn-type="corresp">
          <p>Corresponding author: Vyacheslav A. Kharchenko (vakh41@mail.ru)</p>
        </fn>
      </author-notes>
      <pub-date pub-type="collection">
        <year>2019</year>
      </pub-date>
      <pub-date pub-type="epub">
        <day>01</day>
        <month>03</month>
        <year>2019</year>
      </pub-date>
      <volume>5</volume>
      <issue>1</issue>
      <fpage>1</fpage>
      <lpage>11</lpage>
      <uri content-type="arpha" xlink:href="http://openbiodiv.net/888E8273-2715-598A-AEF6-BBCCA7C74B08">888E8273-2715-598A-AEF6-BBCCA7C74B08</uri>
      <history>
        <date date-type="received">
          <day>29</day>
          <month>04</month>
          <year>2018</year>
        </date>
        <date date-type="accepted">
          <day>21</day>
          <month>05</month>
          <year>2018</year>
        </date>
      </history>
      <permissions>
        <copyright-statement>Vyacheslav A. Kharchenko</copyright-statement>
        <license license-type="creative-commons-attribution" xlink:href="http://creativecommons.org/licenses/by/4.0/" xlink:type="simple">
          <license-p>This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.</license-p>
        </license>
      </permissions>
      <abstract>
        <label>Abstract</label>
        <p>Gettering of rapidly diffusing metallic impurities and structural defects in silicon which is the main material for IC fabrication, high-power high-voltage devices and neutron doped silicon has been studied. Structural defect based getters and gas phase getters based on chlorine containing compounds have been analyzed. Formation of structural defect based getters requires producing intrinsic sources of dislocation generation and precipitate/dislocation agglomerate formation. We show that dislocations are generated at microcrack mouths and form a low-mobility dislocation network at inactive wafer sides. In the latter case the defects are generated in the wafer region adjacent to the active layer of the electronic component. The generation of intrinsic getters is based on the decomposition of the supersaturated oxygen solid solution in silicon which favors the formation of a complex defect system in silicon that consists of various precipitate/dislocation agglomerates. Stacking faults also form, i.e., oxide precipitates with Frank’s dislocation loop clouds. Two intrinsic getter formation methods have been considered: one is related to oxygen impurity drain from the wafer surface region and the other implies accurate control of vacancy distribution over wafer thickness. We have analyzed the effect of getters as defect structures on the reduction of the mechanical stress required for dislocation generation onset which may eventually determine the mechanical strength of silicon wafers.</p>
        <p>The mechanism of impurity and defect gettering by gas phase medium with chlorine-containing compound additions has been considered. We show that silicon atom interaction with chlorine in the surface wafer region at high temperatures may cause the formation of vacancies which may penetrate to the specimen bulk with some probability. This leads to the case ∆<italic>С<sub>v</sub></italic> &gt; 0 and ∆<italic>C<sub>i</sub></italic> ≤ 0, which changes the composition and density of the microdefects. Examples have been given for practical use of heat treatment of silicon wafers in a chlorine-containing atmosphere during oxide film application with the aim to dissolve microdefects, drain rapidly diffusing impurities from crystal bulk and prevent the formation of generation/recombination centers during device fabrication and silicon neutron doping.</p>
      </abstract>
      <kwd-group>
        <label>Keywords</label>
        <kwd>single crystal silicon</kwd>
        <kwd>rapidly diffusing impurities</kwd>
        <kwd>structural defects</kwd>
        <kwd>getters</kwd>
        <kwd>dislocation sources</kwd>
        <kwd>chlorine-containing atmosphere</kwd>
      </kwd-group>
    </article-meta>
  </front>
  <body>
    <sec sec-type="1. Introduction" id="SECID0EFD">
      <title>1. Introduction</title>
      <p>Modern silicon base component fabrication processes widely use the gettering of impurities and structural defects which deleteriously affect the electrical parameters of the devices [<xref ref-type="bibr" rid="B1">1</xref>]. These impurities are primarily Fe, Cu, Ni, Zn, Cr, Au, Hg, Ag etc. [<xref ref-type="bibr" rid="B2">2</xref>, <xref ref-type="bibr" rid="B3">3</xref>]. The main sources of silicon wafer contamination with these impurities are bulk impurities forming during single crystal silicon growth and wafer fabrication as well as micro- and nanoparticles, chemical elements and their compounds remaining on the surface of the wafers after thorough cleaning. Furthermore, rapidly diffusing impurities are efficiently adsorbed by the wafer surface from the working media (vacuum, liquids and vapor or gas atmospheres). During further high-temperature process operations the impurities from the surface layer penetrate intensely to the surface region reaching significant depths. (The diffusion coefficients of metallic impurities are 3–4 orders of magnitude greater than the diffusion coefficients of doping impurities.) Metallic impurities penetrating into the working part of silicon wafers combine with structural defects to form generation/recombination centers which are a major cause of the increase in the leakage current [<xref ref-type="bibr" rid="B2">2</xref>, <xref ref-type="bibr" rid="B4">4</xref>, <xref ref-type="bibr" rid="B5">5</xref>]. This causes the degradation of a wide range of device parameters. In other words, the presence of metallic impurities in the crystal and on its surface is critical for a number of electronic components. Some applications require silicon wafers contain a bulk concentration of e.g. Fe of max. 1×10<sup>10</sup> cm<sup>-3</sup>, the surface impurity concentration also being controlled (less than 1×10<sup>11</sup> cm<sup>-2</sup>) [<xref ref-type="bibr" rid="B1">1</xref>, <xref ref-type="bibr" rid="B6">6</xref>]. These requirements are most critical for ICs with design rules of about decades of nanometers or less, low working currents and voltages and extremely low self-noise. Despite the large background of studies aimed at increasing the cleaning efficiency of as-grown wafers and process environments and providing cleanliness of process operations, the probability of silicon wafer contamination with detrimental rapidly diffusing impurities remains high. It should be noted that the development of absolutely clean conditions in the design of electronic structure processes, especially high-temperature ones, is a complex task for a number of technical and economic reasons. Therefore the probability of the formation of intrinsic point defects and their clusters including those with impurity atoms (e.g. generation/recombination centers) remains high. Thus gettering is primarily used nowadays for preventing the penetration of contaminating impurities into silicon wafer bulk and the formation of generation/recombination centers in the working regions of electronic structures fabricated. Below we will consider process techniques used for the formation of different origin gettering centers, their advantages and drawbacks and redistribution mechanisms of rapidly diffusing impurities and structural defects in silicon wafer bulk.</p>
    </sec>
    <sec sec-type="2. Structural defect base getters" id="SECID0EVE">
      <title>2. Structural defect base getters</title>
      <sec sec-type="2.1 Extrinsic getters" id="SECID0EZE">
        <title>2.1 Extrinsic getters</title>
        <p>Structural defect base getters are divided into extrinsic and intrinsic ones depending on their location in wafer bulk. Earlier when wafer diameters and thicknesses were smaller than now (300 mm or greater) external getter formation methods were intensely developed. An extrinsic getter is a layer with damaged structure mainly consisting of dislocations. Bulk gettering localizes most of the contaminating impurities which do not affect the parameters of electronic structures anymore. The most efficient extrinsic getter is a damaged layer in the form of a low-mobility dislocation network (Fig. <xref ref-type="fig" rid="F1">1</xref>) [<xref ref-type="bibr" rid="B7">7</xref>]. This defect structure is produced by free abrasive grinding of wafer surfaces resulting in the formation of a damaged layer with microcracks. Then dislocation pile-ups form at the mouths of these microcracks due to high mechanical stresses during further heat treatment at ~750 °C in an argon atmosphere. The dislocation density in the pile-ups may be as high as 10<sup>9</sup>–10<sup>12</sup> cm<sup>-2</sup>. Dislocation pinning in the form of a dislocation network occurs by dislocation climb due to interaction with interstitial silicon atoms that are generated during the abovementioned heat treatment as a result of local decomposition of the supersaturated oxygen solid solution (oxygen concentration in silicon reaches ~ (7–9)×10<sup>17</sup> cm<sup>-3</sup>). Other efficient damaged layer production methods are surface plasma treatment, deposition of films of different materials, deposition of polycrystalline silicon, ion bombardment etc. [<xref ref-type="bibr" rid="B1">1</xref>]. There is also a special damaged layer production method in inactive wafer regions by high-energy laser irradiation [<xref ref-type="bibr" rid="B8 B9 B10 B11">8–11</xref>]. After irradiation the wafers are annealed with the aim to form a dislocation structure with the required in-layer defect density. The greatest gettering efficiency is achieved for damaged layer depths of within 5–10 μm (at laser energy density of 9–15 J/cm<sup>2</sup>).</p>
        <fig id="F1" position="float" orientation="portrait">
          <object-id content-type="arpha">92FF484E-9950-52B2-84B4-BD06E4700A05</object-id>
          <label>Figure 1.</label>
          <caption>
            <p>Dislocation networks in silicon wafers after grinding and heat treatment [<xref ref-type="bibr" rid="B7">7</xref>]. (a) Dislocation network generation at microcrack mouth and (b) well-developed hexagonal dislocation network.</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g001.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363826.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363826</uri>
          </graphic>
        </fig>
      </sec>
      <sec sec-type="2.2 Intrinsic getters" id="SECID0EHG">
        <title>2.2 Intrinsic getters</title>
        <p>Intrinsic getters differ in nature from extrinsic ones, primarily by the type of structural defects and getter location: they are typically located at a certain distance from the working side of the wafer. The damaged layer is a group of structural defects in the form of oxygen precipitate/dislocation agglomerates and stacking faults. The formation of the damaged layer is caused by the well-studied decomposition of supersaturated oxygen solid solution which is always present in Czochralski grown crystals [<xref ref-type="bibr" rid="B12">12</xref>]. Typical damaged layer formation process includes four heat treatments of as-grown silicon wafers:</p>
        <list list-type="bullet">
          <list-item>
            <p>first heat treatment (1000 °C, 15 min): diffusion-induced oxygen depletion of wafer surface layer and bulk dissolution of small “growth” precipitates;</p>
          </list-item>
          <list-item>
            <p>second heat treatment (650 °C, 16 h): homogeneous oxygen precipitation;</p>
          </list-item>
          <list-item>
            <p>third heat treatment (800 °C, 4 h): precipitate growth and coalescence;</p>
          </list-item>
          <list-item>
            <p>fourth heat treatment (1000 °C, 4 h): precipitate growth to the required sizes [7, 13].</p>
          </list-item>
        </list>
        <p>As the precipitates reach 60–70 nm in size, intense formation of dislocation loops starts at plate-shaped precipitate boundaries, the dislocation loops propagating from the precipitates to the adjacent bulk regions along the slip planes by prismatic extrusion. After that the dislocation loops form complex 3D dislocation pile-ups, e.g. by climb of some dislocations to other crystallographic planes. Furthermore, the decomposition of supersaturated oxygen solid solution also causes the formation of a large number of stacking faults in the form of Frank’s dislocation loops with oxide precipitates in the stacking fault centers. Thus this intrinsic getter formation method produces an up to 30–50 μm depth surface region that does not contain extrinsic defects. The bulk density of the precipitates reaches approx. 10<sup>11</sup> cm<sup>-3</sup> which is sufficient for efficient gettering.</p>
        <p>The difference of another possible intrinsic getter formation method is the absence of the first high-temperature stage for oxygen draining from the wafer surface region, with the defect region location being controlled by providing the required vacancy distribution profile [<xref ref-type="bibr" rid="B14">14</xref>]. The required profile is produced by rapid thermal annealing at 1200 °C for 4 h. The getter then forms as a result of heat treatment at 800 °C for 4 h and subsequent heat treatment at 1000 °C for 16 h [<xref ref-type="bibr" rid="B7">7</xref>]. This intrinsic getter formation method is based on the large dependence of the decomposition of supersaturated oxygen solid solution on vacancy concentration [<xref ref-type="bibr" rid="B15 B16 B17">15–17</xref>]. Thus rapid annealing reduces the vacancy concentration in the wafer surface region to below a certain critical level (≤10<sup>12</sup> cm<sup>-3</sup>). Hence the decomposition of supersaturated oxygen solid solution is almost completely suppressed in this region. The vacancy concentration in the rest of the wafer bulk is far above the critical level, and the supersaturated oxygen solid solution decomposes quite intensely. Figure <xref ref-type="fig" rid="F2">2</xref> shows an intrinsic getter in wafer bulk formed by structural defects, and Fig. <xref ref-type="fig" rid="F3">3</xref> shows wafer depth defect density distribution [<xref ref-type="bibr" rid="B18">18</xref>]. This getter formation method produces an up to 50–80 μm depth defect free surface region, the bulk precipitate density reaching 8 · 10<sup>9</sup> cm<sup>-3</sup>. In some cases efficient gettering can be achieved at precipitate densities of ~ (3–8) · 10<sup>7</sup> cm<sup>-3</sup>.</p>
        <fig id="F2" position="float" orientation="portrait">
          <object-id content-type="arpha">96EF1474-1D0A-5249-B09A-2B29A16A5C9F</object-id>
          <label>Figure 2.</label>
          <caption>
            <p>Microdefect distribution on transverse cleaves of silicon wafers after three-stage heat treatment for intrinsic getter formation [<xref ref-type="bibr" rid="B18">18</xref>].</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g002.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363827.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363827</uri>
          </graphic>
        </fig>
        <fig id="F3" position="float" orientation="portrait">
          <object-id content-type="arpha">1F1A6AF8-585E-525A-A9F2-7EC096454D0F</object-id>
          <label>Figure 3.</label>
          <caption>
            <p>Microdefect density N as a function of wafer depth <italic>t</italic> for internal getter formation [<xref ref-type="bibr" rid="B18">18</xref>].</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g003.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363828.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363828</uri>
          </graphic>
        </fig>
        <p>It should be noted that intrinsic getter formation using the method described above is quite efficient for Czochralski grown silicon wafers. Producing the required density of oxygen precipitate/dislocation agglomerates in zone melting grown silicon wafers is complicated due to the insufficient oxygen content for this silicon growth method. Therefore a special process has been developed for introducing the required oxygen concentration into zone melting grown silicon wafers by ion implantation. It has been reported [<xref ref-type="bibr" rid="B19">19</xref>] that the efficiency of impurity precipitate/dislocation agglomerate formation increases considerably if carbon atoms are preliminarily implanted into silicon wafers.</p>
      </sec>
      <sec sec-type="2.3 Dislocation generation" id="SECID0EQBAC">
        <title>2.3 Dislocation generation</title>
        <p>It should be noted that silicon wafers with extrinsic or intrinsic getters are metastable and characterized by strong internal mechanical stress. This stress favors accelerated impurity atom and intrinsic point defect migration towards the getters. In the meantime different types of intrinsic dislocation generation sources are retained in the vicinity of the getters. Therefore high-temperature heat treatment or epitaxy as well as external load application to devices during operation dramatically increase the probability of dislocation generation in as-grown wafer bulk and in the devices thus significantly compromising the electrophysical parameters and mechanical strength of the material. Below are experimental examples of dislocation generation intensity as a function of the size and structure of microdefects forming during the decomposition of supersaturated oxygen solid solution at different heat treatment modes and under external loads [<xref ref-type="bibr" rid="B20">20</xref>]. The mechanical stress causing dislocation generation from intrinsic sources was determined from dislocation generation onset. Figure <xref ref-type="fig" rid="F4">4</xref> [<xref ref-type="bibr" rid="B20">20</xref>] shows intrinsic source dislocation generation mechanical stress σ<sub>gen</sub> for specimens after different heat treatment modes used for intrinsic getter formation. It can be seen from Fig. <xref ref-type="fig" rid="F4">4</xref> that multistage heat treatment for intrinsic getter formation in silicon wafers causes noticeable loss in their mechanical strength. In the specimens of Series 1–3, 4 and 5 presented, the shear mechanical stresses σ<sub>gen</sub> differ by approx. five times, and for Series 4 and 5 these stresses are several times lower than in the as-grown specimens. Additional transmission electron microscopy studies of dislocation generation and migration in the specimens heat treated for getter formation under external mechanical loads showed that the strength loss magnitude depends on the nature, size and density of the defects. The most efficient heterogeneous dislocation generation centers are large stacking fault type microdefects, dislocation dipoles (Fig. <xref ref-type="fig" rid="F5">5</xref><italic>a</italic>) and linear dislocation/precipitate agglomerates (Fig. <xref ref-type="fig" rid="F5">5</xref><italic>b</italic>). The application of external loads generates prismatic dislocations; as a result the total size of the microdefects grows more than twofold and the dislocation loop scatter from these microdefects reaches several millimeters [<xref ref-type="bibr" rid="B20">20</xref>]. It should be noted that growth microdefects that are inevitable in the as-grown crystals may also act as efficient dislocation getters (Fig. <xref ref-type="fig" rid="F6">6</xref>) [<xref ref-type="bibr" rid="B21">21</xref>]. Thus the dislocations generated by internal sources under external impact may penetrate to the working region of wafers (or devices) and cause degradation of the electrical parameters.</p>
        <fig id="F4" position="float" orientation="portrait">
          <object-id content-type="arpha">D8A8C944-AD09-5DEA-8F3D-606AC59AE5D8</object-id>
          <label>Figure 4.</label>
          <caption>
            <p>Shear stress threshold for dislocation generation from internal source for silicon specimens heat treated in different modes [<xref ref-type="bibr" rid="B20">20</xref>]: (<italic>1</italic>) as-grown; (<italic>2</italic>) 1000 °C/15 min + 450 °C/16 h; (<italic>3</italic>) 1000 °C/15 min + 650 °C/16 h; (<italic>4</italic>) 1000 °C/15 min + 650 °C/16 h + 800 °C/4 h + 1000 °C/4 h; (<italic>5</italic>) 1000 °C/15 min + 450 °C/16 h + 650 °C/16 h + 1000 °C/4 h.</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g004.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363829.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363829</uri>
          </graphic>
        </fig>
        <fig id="F5" position="float" orientation="portrait">
          <object-id content-type="arpha">AD2FFD05-A899-57DE-BE63-A9DF98866A3D</object-id>
          <label>Figure 5.</label>
          <caption>
            <p>(a) Loop-generating dislocation dipole type microdefects and (b) globular dislocation/precipitate agglomerates.</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g005.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363830.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363830</uri>
          </graphic>
        </fig>
        <fig id="F6" position="float" orientation="portrait">
          <object-id content-type="arpha">19F267BE-39E9-5695-B2E2-39A8CB6A0E99</object-id>
          <label>Figure 6.</label>
          <caption>
            <p>(a, b) Microdefects in zone melting grown single crystal silicon and (c, d) dislocation generation under pressure [<xref ref-type="bibr" rid="B21">21</xref>]: (a) A type microdefects; (b) B type microdefects.</p>
          </caption>
          <graphic xlink:href="moem-05-e38575-g006.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363831.jpg">
            <uri content-type="original_file">https://binary.pensoft.net/fig/363831</uri>
          </graphic>
        </fig>
        <p>Note that under specific conditions, e.g. during partial recrystallization of the damaged layer, the getters considered herein may return impurity atoms to the bulk, i.e., recontamination of the cleaned regions is possible.</p>
      </sec>
    </sec>
    <sec sec-type="3. Gas phase base getters" id="SECID0ESEAC">
      <title>3. Gas phase base getters</title>
      <p>Gas phase gettering implies heat treatment of wafers and bulk specimens in vacuum and inert and chlorine-containing atmospheres. This method is based on point defect and impurity atom extraction from wafer bulk to gas phase or vacuum.</p>
      <p>An illustrative example of gas phase impurity gettering is oxygen impurity drain from the surface regions of silicon wafers (see above). This process is accompanied by sublimation of surface silicon atoms. Possibly the silicon/impurity system is depleted of the more volatile component more intensely during evaporation. Silicon and impurity sublimation leads to vacancy formation on the surface and in the surface region thus destroying the equilibrium of the vacancies and the interstitial atoms between the surface and the bulk. This results in diffusion of interstitial atoms and vacancies toward the surface and further to the gas atmosphere. The density of the structural microdefects consisting of interstitial atoms, including stacking faults, decreases due to the supply of vacancies. This process is typical of wafer heat treatment at 800–1200 °C in an argon gas atmosphere. As a result the surface wafer layer becomes almost free of primary microdefects and thus the formation of oxidation induced stacking faults is suppressed during the further growth of the oxide film.</p>
    </sec>
    <sec sec-type="4. Gettering in chlorine-containing atmosphere with HCl addition" id="SECID0E4EAC">
      <title>4. Gettering in chlorine-containing atmosphere with HCl addition</title>
      <p>Gettering in a chlorine-containing atmosphere with hydrogen chloride addition is most often used for heat treatment of microelectronics components in order to control microdefect composition and impurity content in silicon wafer bulk. We will consider below the evolution of point defect clusters during active chemical hydrogen chloride etching of silicon wafers. According to earlier data [<xref ref-type="bibr" rid="B22">22</xref>, <xref ref-type="bibr" rid="B23">23</xref>], the basic etching process includes several stages:</p>
      <list list-type="bullet">
        <list-item>
          <p>molecular HCl chemisorption;</p>
        </list-item>
        <list-item>
          <p>formation of H–Si–Cl type intermediate surface complexes;</p>
        </list-item>
        <list-item>
          <p>transformation of the complexes, through the formation of intermediate chemical compound SiCl 2 and its interaction with HCl, to primary reaction products: silicon tetrachloride, tricholsilane, dichlorsilane etc.;</p>
        </list-item>
        <list-item>
          <p>desorption of the primary products from silicon surface.</p>
        </list-item>
      </list>
      <p>The chlorine/silicon interaction reactions are exothermal, favoring a significant weakening of the bonds between the reacting silicon atoms in the crystalline structure. The metal and carbon impurities on the surface and in the surface region are efficient catalysts of silicon chloride formation reactions. Metals also form volatile chlorides. Oxygen and water steam supplied to the specimen surface have a negative effect on chloride formation.</p>
      <p>Primary silicon atom removal from the surface wafer layer during HCl etching results in the formation of vacancies (<italic>V</italic>) which have a low but still meaningful probability of diffusing into wafer bulk [<xref ref-type="bibr" rid="B24">24</xref>]. The generation of metastable vacancies from the surface leads to the formation of a supersaturated solid solution of <italic>V</italic> in the bulk, accompanied by the formation of a diluted solid solution of other defect type. As reported earlier [<xref ref-type="bibr" rid="B25">25</xref>] this nonequilibrium situation takes place if ∆<italic>С<sub>v</sub></italic> &gt; 0, ∆<italic>C<sub>i</sub></italic> ≤0. Then <italic>V</italic> interaction with microdefects consisting of interstitial atoms reduces the microdefect size until complete dissolution. More complete data on the interaction between point defects and microdefects in silicon were reported elsewhere [<xref ref-type="bibr" rid="B26 B27 B28">26–28</xref>].</p>
      <p>Experimental confirmation of A cluster type microdefect annihilation and oxidation induced stacking fault density reduction in silicon specimens after heat treatment in chlorine-containing atmosphere was reported earlier [<xref ref-type="bibr" rid="B29 B30">29–30</xref>]. Figure <xref ref-type="fig" rid="F7">7</xref> shows macro- and microdistribution of A clusters in the as-grown specimens and specimens heat treated in a chlorine-containing atmosphere. The A clusters had a swirl-type distribution in the as-grown specimen. The heat treatment parameters were 1200 °C, 8 min, in an H<sub>2</sub> + HCl atmosphere. After this heat treatment selective etching revealed no A clusters in the silicon specimens, and this was additionally confirmed by the absence of oxidation induced stacking faults after subsequent oxidation.</p>
      <fig id="F7" position="float" orientation="portrait">
        <object-id content-type="arpha">8E7F8271-9B18-5C74-BECD-DD93C0A5DA12</object-id>
        <label>Figure 7.</label>
        <caption>
          <p>Macro (top) and micro (bottom) distribution of structural defects in (a) as-grown specimen and (b) specimen after heat treatment in a chlorine-containing atmosphere [<xref ref-type="bibr" rid="B25">25</xref>]. Heat treatment parameters: 1200 °C, 8 min, H<sub>2</sub> + HCl atmosphere.</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g007.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363832.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363832</uri>
        </graphic>
      </fig>
      <p>Heat treatment in a chlorine-containing atmosphere has also found practical application for oxide film growth on silicon wafers. Note that SiO<sub>2</sub> films grown by thermal oxidation, e.g. for MOS (metal/oxide/semiconductor) structures, does not always satisfy the strict requirements to surface charge, surface recombination rate and bulk trap concentration (more than 10<sup>16</sup> cm<sup>-3</sup>). It was reported that the degradation of these parameters is mainly caused by alkaline metal contamination of the material during high-temperature oxidation [<xref ref-type="bibr" rid="B31">31</xref>, <xref ref-type="bibr" rid="B32">32</xref>]. A promising solution was to eliminate the effect of alkaline metals by adding HCl to the oxidizing atmosphere. Much chlorine is adsorbed by the growing oxide which is then strongly bound with mobile alkaline metal ions. It is probably due to their large size that chlorine ions are almost immobilized in the SiO<sub>2</sub> matrix and hence strongly bind mobile alkaline metal ions. Practical result are high-quality 5–100 nm thick SiO<sub>2</sub> films grown by two-stage dry oxidation with ~1–3% HCl addition.</p>
    </sec>
    <sec sec-type="5. Gettering in CCl4 (C2HCl3) base chlorine-containing atmosphere" id="SECID0EAIAC">
      <title>5. Gettering in CCl<sub>4</sub> (C<sub>2</sub>HCl<sub>3</sub>) base chlorine-containing atmosphere</title>
      <p>Impurity and defect gettering in a chlorine-containing atmosphere finds general use in the fabrication of high-power high-voltage devices with the source material being zone melting grown dislocation-free single crystal silicon. The oxygen impurity concentration in this silicon is several orders of magnitude lower than in Czochralski grown silicon which is the main material of microelectronics. Moreover the working region of high-power devices covers the entire wafer bulk. Therefore getter formation on the basis of structural defects in zone melting grown silicon wafers for high-power devices is impossible. The problem of gettering microdefects and rapidly diffusing metallic impurities in zone melting grown silicon wafers proved to be solvable by using heat treatment in a CCl<sub>4</sub> base chlorine-containing atmosphere. By way of example Fig. <xref ref-type="fig" rid="F8">8</xref> illustrates the effect of heat treatment atmosphere on microdefect evolution in zone melting grown bulk silicon crystals [<xref ref-type="bibr" rid="B33">33</xref>]. In the as-grown state the microdefects are distributed in the crystal bulk in the form of swirls (Fig. <xref ref-type="fig" rid="F8">8</xref><italic>a</italic>), and after heat treatment in a chlorine-containing atmosphere at 1250 °C for 40 h no microdefects were not found in these crystals (Fig. <xref ref-type="fig" rid="F8">8</xref><italic>b</italic>). Similar heat treatment of the reference specimens in air caused an increase in the microdefect size and density and a growth of swirl strips. This indicates drain of metastable intrinsic defects and impurity atoms to the as-grown microdefects. The chlorine-containing atmosphere used in these experiments was an argon and oxygen mixture with ~1 mol.% CCl<sub>4</sub> vapor addition. More detailed studies of chlorine-containing atmosphere heat treatment efficiency for microdefect-containing silicon crystals, including those with swirl-type distribution, were reported earlier [<xref ref-type="bibr" rid="B34">34</xref>, <xref ref-type="bibr" rid="B35">35</xref>].</p>
      <fig id="F8" position="float" orientation="portrait">
        <object-id content-type="arpha">09FEFBD7-94F5-5704-940A-C0A6D3E4BA98</object-id>
        <label>Figure 8.</label>
        <caption>
          <p>(a) Selective microdefect etching in as-grown silicon specimen with swirl microdefect distribution and (b) selective etching of silicon specimen after heat treatment in a chlorine-containing atmosphere at 1250 °C for 40 h [<xref ref-type="bibr" rid="B33">33</xref>]. Specimens are zone melt grown.</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g008.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363833.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363833</uri>
        </graphic>
      </fig>
      <p>Another efficient application of heat treatment in a chlorine-containing atmosphere is radiation induced defect annealing in the neutron doped silicon technology. The source material for neutron doping is zone melt grown single crystal dislocation-free silicon. The specially prepared silicon ingots are neutron irradiated in a thermal neutron reactor. Detailed description of the neutron doping process of semiconductor materials was reported earlier [<xref ref-type="bibr" rid="B36">36</xref>]. Thermal neutron reactions</p>
      <p>Si<sup>30</sup>(<italic>n</italic>,γ)Si<sup>31</sup>(β<sup>-</sup>-decay) → P<sup>31</sup></p>
      <p>produce phosphorus atoms that are a donor impurity in silicon. Along with P<sup>31</sup> atoms, a large number of accompanying radiation induced defects are generated in the doped silicon crystals as a result of bombardment with nuclear debris, fast (high-energy) neutrons and γ-particles and due to recoil atoms. As-irradiated ingots are heat treated at high temperatures for eliminating the negative effect of the radiation induced defects on the electrophysical properties. The completeness of radiation induced defect annealing is judged about by the recovery of the electrophysical parameters of the material, primarily the electrical resistivity ρ and minority carrier lifetime τ. It was shown that heat treatment at 800–900 °C for ~2 h recovers ρ to the target level, with τ always being several times lower than the initial level, sometimes even below the acceptable level. Despite the large number of studies [<xref ref-type="bibr" rid="B36">36</xref>] the τ recovery problem could not be solved for a long time until the effect of annealing atmosphere on microdefect transformation and change in bulk content of rapidly diffusing impurity was revealed. One of the earliest works on this theme showed that τ differs significantly depending on annealing atmosphere (Fig. <xref ref-type="fig" rid="F9">9</xref>) [<xref ref-type="bibr" rid="B37">37</xref>].</p>
      <fig id="F9" position="float" orientation="portrait">
        <object-id content-type="arpha">94BF65BA-10A5-5375-97B1-9F0AEC9CC2BA</object-id>
        <label>Figure 9.</label>
        <caption>
          <p>Effect of annealing atmosphere on minority carrier lifetime in neutron doped silicon specimens [<xref ref-type="bibr" rid="B37">37</xref>]. Annealing at 850 °C for 4 h.</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g009.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363834.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363834</uri>
        </graphic>
      </fig>
      <p>The highest τ are observed in specimens heat treated in a chlorine-containing atmosphere; air, vacuum and argon heat treated specimens follow in order of decreasing τ. It should be noted that τ degradation depends on microdefect density and presence of rapidly diffusing metallic impurity atoms in crystals. By way of example Fig. <xref ref-type="fig" rid="F10">10</xref> shows τ as a function of microdefect density in neutron doped silicon heat treated in air [<xref ref-type="bibr" rid="B38">38</xref>] and Fig. <xref ref-type="fig" rid="F12">11</xref> shows bulk τ distribution depending on gold atom profile in similar specimens heat treated in air and in a chlorine-containing atmosphere [<xref ref-type="bibr" rid="B39">39</xref>]. Gold was deposited on specimen butts after neutron irradiation before annealing. Noteworthy is the appearance of microdefects in some silicon specimens after irradiation and heat treatment in air in which τ were low [<xref ref-type="bibr" rid="B40">40</xref>, <xref ref-type="bibr" rid="B41">41</xref>]. No microdefects were found in these as-grown ingots before irradiation and τ were sufficiently high. Note also that τ in specimens heat treated in a chlorine-containing atmosphere increase monotonically in depth (Fig. <xref ref-type="fig" rid="F12">11</xref><italic>b</italic>) and drastically reach the as-grown ~1000 μs level beginning from a 3 mm depth unlike for air heat treated specimens in which τ reach 200–400 μs at best.</p>
      <fig id="F10" position="float" orientation="portrait">
        <object-id content-type="arpha">33731ACB-2CF9-5627-93D3-459581697900</object-id>
        <label>Figure 10.</label>
        <caption>
          <p>Minority carrier lifetime as a function of microdefect density in neutron doped silicon [<xref ref-type="bibr" rid="B38">38</xref>].</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g010.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363835.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363835</uri>
        </graphic>
      </fig>
      <fig id="F12" position="float" orientation="portrait">
        <object-id content-type="arpha">7DBA3CEA-F96D-5465-BF34-06CA0652E982</object-id>
        <label>Figure 11.</label>
        <caption>
          <p>Minority carrier lifetime as a function of gold atom distribution in silicon specimen bulk after heat treatment in (<italic>a</italic>) air and (<italic>b</italic>) chlorine-containing atmosphere [<xref ref-type="bibr" rid="B39">39</xref>]: (<italic>1</italic>) “clean” specimen butt; (<italic>2</italic>) gold-plated specimen butt.</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g012.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363836.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363836</uri>
        </graphic>
      </fig>
      <p>Thus gas phase gettering solves the following tasks:</p>
      <list list-type="bullet">
        <list-item>
          <p>τ recovery in silicon specimens by heat treatment in a chlorine-containing atmosphere to significant levels if as-grown τ do not satisfy the requirements;</p>
        </list-item>
        <list-item>
          <p>microdefect composition and density control in as-grown silicon specimens for oxidation or other similar process operations;</p>
        </list-item>
        <list-item>
          <p>prevention of generation/recombination center formation and metallic impurity atom penetration into silicon specimen bulk after different heat treatments in electronic device processes and during neutron doping.</p>
        </list-item>
      </list>
      <p>Below we will consider possible methods of microdefect composition controlling and τ recovery.</p>
    </sec>
    <sec sec-type="6. Generation/Recombination center transformation mechanisms" id="SECID0EPNAC">
      <title>6. Generation/Recombination center transformation mechanisms</title>
      <p>It was shown above that generation/recombination centers are complex agglomerates of the microdefect + metal impurity atom type. The microdefects may have variable dimensions and mainly consist of interstitial atoms. It can therefore be concluded that introducing a nonequilibrium vacancy concentration into crystal bulk might help destroying the generation/recombination centers due to vacancy interactions with interstitial atoms in the microdefects. Note that heat treatment induces complex processes in silicon crystals including generation and recombination of intrinsic point defects and their interaction with different types of structural defects. They generally include the following:</p>
      <list list-type="bullet">
        <list-item>
          <p>high-temperature point defect generation and recombination in crystalline lattice;</p>
        </list-item>
        <list-item>
          <p>point defect emission and incorporation in microdefects;</p>
        </list-item>
        <list-item>
          <p>point defect generation and recombination on crystal surface causing generation of bulk – surface and vice versa diffusion flows;</p>
        </list-item>
        <list-item>
          <p>precipitate formation due to point defect interaction with one another and with impurity atoms;</p>
        </list-item>
        <list-item>
          <p>radiation induced point defect generation and recombination.</p>
        </list-item>
      </list>
      <p>The most complete analysis of the interactions occurring in this system was reported elsewhere [<xref ref-type="bibr" rid="B25">25</xref>]. Taking into account those data we will consider specific examples of microdefect transformation depending on heat treatment conditions.</p>
      <p>Oxidation induced stacking fault size evolution during heat treatment in argon and in hydrogen as well as during thermal oxidation is shown as a function of exposure time in Fig. <xref ref-type="fig" rid="F11">12</xref> [<xref ref-type="bibr" rid="B25">25</xref>]. It can be seen from Fig. <xref ref-type="fig" rid="F11">12</xref> that heat treatment in argon and in hydrogen (Curves <italic>1</italic> and <italic>2</italic>) gradually reduces the size of the oxidation induced stacking faults, the reduction being temperature-dependent. These data suggest that heat treatment in argon and in hydrogen at best retains the defect structure in silicon specimens close to the as-grown one although microdefect sizes change. Thus the system is slightly supersaturated with vacancies.</p>
      <fig id="F11" position="float" orientation="portrait">
        <object-id content-type="arpha">9C50F3DD-E941-5ECC-8161-E6F4C529B73D</object-id>
        <label>Figure 12.</label>
        <caption>
          <p>Change in size of oxidation induced stacking faults after heat treatment in (<italic>1</italic>) argon and (<italic>2</italic>) hydrogen and (<italic>3, 4</italic>) thermal oxidation [<xref ref-type="bibr" rid="B25">25</xref>]. Heat treatment temperatures, °C: (<italic>1</italic>, <italic>3</italic>) 1100 °C; (<italic>2</italic>, <italic>4</italic>) 1150 °C.</p>
        </caption>
        <graphic xlink:href="moem-05-e38575-g011.jpg" position="float" orientation="portrait" xlink:type="simple" id="oo_363837.jpg">
          <uri content-type="original_file">https://binary.pensoft.net/fig/363837</uri>
        </graphic>
      </fig>
      <p>In turn the oxidation induced stacking fault sizes grow quite rapidly during heat treatment (Curves <italic>3</italic> and <italic>4</italic>), the growth being slightly temperature-dependent. Presumably interstitial atoms dominate in the system. This nonequilibrium situation is described by the ratio ∆<italic>С<sub>v</sub></italic> ≤ 0, ∆<italic>C<sub>i</sub></italic> &gt; 0. In other words the oxidation induced interstitial silicon atoms condensate intensely on microdefects, their size and density increasing as a result. An efficient source of nonequilibrium interstitial atoms is in this case the thermally oxidized silicon surface. A similar situation occurs in neutron doped silicon during air annealing: some crystals exhibit microdefect size and density growth. These crystals usually have a short carrier lifetime. Note that the origin of microdefect growth is associated with the precursor defects forming during single crystal growth and having small sizes in the as-grown state thus having a negligible effect on lattice deformation. Taking into account this observation one should preliminarily dissolve the precursor defects in order to avoid the formation of oxidation induced stacking faults in silicon specimens which will undergo oxidation. In other words additional heat treatment is intended to produce a supersaturated vacancy solid solution in the crystals: ∆<italic>С<sub>v</sub></italic> &gt; 0, ∆<italic>C<sub>i</sub></italic> ≤ 0. As shown above, this method is implemented using heat treatment in a chlorine-containing atmosphere, e.g. HCl.</p>
      <p>The interaction mechanism between the structural defects in neutron doped silicon is more complex since it develops in the presence of radiation induced defects the structure of which is incompletely clear. Assuming that neutron irradiation does not produce disordered regions with amorphization traces one can safely hypothesize that the radiation defects mainly contain point defects and their complexes including those with impurity atoms inherited from the as-grown ingots or formed as a result of nuclear reactions. This makes it possible that the condition ∆<italic>С<sub>v</sub></italic> &gt; 0, ∆<italic>C<sub>i</sub></italic> &gt; 0 is true. At an early stage of heat treatment in a chlorine-containing atmosphere part of the radiation induced interstitial atoms recombinate with vacancies while other part migrate to specimen surface due to a higher diffusion coefficient or settle on microdefect surfaces. With a decrease in the nonequilibrium concentration of interstitial atoms at subsequent annealing stage due to chlorine chemical reactions with silicon, the vacancy formation on crystal surface becomes predominant, with the vacancies intensely penetrating into the bulk and interacting with growth microdefects. In this case the relationship ∆<italic>С<sub>I</sub></italic>/∆<italic>С<sub>V</sub></italic> &lt; <italic>D<sub>V</sub></italic>/<italic>D<sub>I</sub></italic> is valid and hence microdefects dissolve. Thus heat treatment of neutron irradiated silicon specimens in a chlorine-containing atmosphere destroys the generation/recombination centers, and the released metallic impurity atoms diffuse over interstitial sites and drain to the surface where they react intensely with chlorine atoms. This mechanism of defect annealing in a chlorine-containing atmosphere is confirmed by earlier experimental data [<xref ref-type="bibr" rid="B39">39</xref>] obtained in a radioactive marker study of gold and iron atom release efficiency from the bulk of silicon specimens heat treated in different atmospheres for radiation induced defect annealing. The test specimens with pre-deposited Au<sup>195</sup> and Fe<sup>59</sup> isotopes onto the butts were heat treated first in air and then in a chlorine-containing atmosphere and a separate series of specimens were only heat treated in the chlorine-containing atmosphere. Air annealing resulted in iron and gold atoms penetration to a 40 μm depth into the bulk. Subsequent heat treatment in a chlorine-containing atmosphere reduced the gold concentration by approx. one order of magnitude and the iron concentration almost by two orders of magnitude at a 15 μm depth. The specimens heat treated in the chlorine-containing atmosphere without preliminary air anneal had only traces of radioactive elements. Thus the possibility of back-diffusion of metallic impurities from the bulk of single crystal silicon specimens is confirmed if certain conditions are met.</p>
    </sec>
    <sec sec-type="7. Conclusion" id="SECID0EKBAE">
      <title>7. Conclusion</title>
      <p>We reviewed results showing that gettering of rapidly diffusing metallic impurities and structural defects is widely used in the fabrication of electronic components on the basis if single crystal silicon. Getters formed on structural defects are dislocation networks in case of extrinsic getters while intrinsic getters consist of oxygen/precipitate dislocation complexes. These getters also contain dislocation generation centers with a high density which during device operation may emit dislocations to the active device regions as a result of contingency external mechanical load application. Furthermore recrystallization may cause recontamination of the device working region with formerly gettered impurities. In either case device degradation is probable.</p>
      <p>In turn, if silicon is supersaturated with vacancies, gas phase getters favor microdefect dissolution, generation/recombination center destruction and rapidly diffusing impurity drain to surface followed by the formation of volatile chlorine compounds. The fundamental difference in the nature of the two getter types shows good promise for improving the reliability of devices fabricated on silicon wafers using heat treatment in chlorine-containing atmospheres.</p>
    </sec>
  </body>
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